Research is accomplished with a multi-disciplinary view of algorithms, architectures, arithmetic, functional units, circuits, VLSI design, applications, and software tools of both programmable and special-purpose processors. We are one of very few university groups in the world that design and fabricate programmable (and configurable special-purpose) processor chips. Our research is grounded in achieving the aforementioned goals on widely-used applications measured in our laboratory on advanced deep-submicron CMOS fabricated chips which we have designed.

We believe we have designed the #1 and #2 highest clock rate fabricated processors and among the largest deep-submicron CMOS chips ever designed in a university.

Current Research & Sponsors

Publications

Projects

Downloadable Tools Developed in the VCL

VCL Laboratory Information

A Few Group Photos

People of the VCL

Faculty
	Professor Bevan Baas
Postdoc
	Dr. Brent Bohnenstiehl
Graduate students
	Derek Li Ph.D. Student Image compression Hardware design Architectures		Basheer Ammar Ph.D. Student Digital Systems Architectures Trigonometric functions
	Yechengnuo Zhang Ph.D. Student Hardware accelerators Hardware design Architectures		Daniel Chevy Ph.D. Student Hardware design Fast Fourier Transforms Architectures
	Michael Wang MS Student Discrete Cosine Transforms Hardware design Architectures		Sagar Sajeev MS Student FPGA design Hardware design Architectures
	Dinesh Nagulapati MS Student Hardware design Digital systems Architectures		Open position MS Student Hardware design Digital systems Architectures
Undergraduate Researchers
	Catherine Kang BS Student Parallel Simulators Programming environments Platform development
Alumni
Ph.D.
	Prof. Zhiyi Yu Ph.D. ECE, Oct. 2007 Associate Professor Sun Yat-Sen and Carnegie Mellon University Network on chip GALS clocking AsAP 1.0 physical design		Prof. Tinoosh Mohsenin Ph.D. ECE, Nov. 2010 Associate Professor Johns Hopkins University LDPC algorithms LDPC architectures and processor design Many-core processor arrays
	Dr. Anh Tran Ph.D. ECE, Aug. 2012 Lead Hardware R&D Engineer Cavium Inc., San Jose On-chip interconnects Multi-core architectures VLSI DSP implementation		Dr. Zhibin Xiao Ph.D. ECE, Dec. 2012 Senior Hardware Engineer Software-in-Silicon R&D Group Oracle Memory system design Video and multimedia applications Processor shapes and topologies
	Prof. Aaron Stillmaker Ph.D. ECE, Dec. 2015 Assistant Professor California State University, Fresno Many-core architecture Physical design Parallel many-core sorting		Dr. Bin Liu Ph.D. ECE, Sep. 2016 Software Engineer Machine Learning Group Uber AES encryption DVFS circuits and algorithms Core scaling
	Dr. Jon Pimentel Ph.D. ECE, Aug. 2017 Silicon Architecture Engineer Many Integrated Core Group Intel Floating-point architecture SAR image processing Sparse matrix multiplication		Dr. Brent Bohnenstiehl Ph.D. ECE, March 2020 Postdoctoral Researcher Processor architectures VLSI Design Software tool development
	Dr. Shifu Wu Ph.D. ECE, Sept. 2021 Intel Image processing Display Stream Compression Algorithm design		Dr. Satyabrata Sarangi Ph.D. ECE, September 2022 Meta Huffman decoders VLSI design Hardware architecture
	Dean Truong ABD Ph.D. MS ECE, May 2010 AsAP2 architecture and chip design DVFS circuits and algorithms Programming tools
	Dr. Forough Mahmoudabadi Research Scientist Device Development Engineer Intel CMOS chip design FD-SOI body bias circuits Full-custom layout
M.S.
	Ryan Apperson MS ECE, Sept. 2004 Senior Electrical Engineer Physio-Control R&D Asynchronous data interfacing circuits SRAM design Full-custom CMOS layout		Omar Sattari gate io, Sept. 2004 Software Engineer     ViaSat Instructor     Allied American University Address generation and branching Programming assembler, config FFT algorithm mapping
	Mike Lai MS ECE, Sept. 2004 Design Engineer Altera High-speed pipelined signed multiplier High-speed modular signed adder Full-custom CMOS layout		Mike Meeuwsen MS ECE, April 2005 Hardware Engineer Intel, Digital Enterprise Group 802.11a algorithm mapping Architectural enhancements Instruction set design
	Toney Jacobson MS ECE, July 2007 Patent Associate Fenwick & West LLP Fast Fourier Transform (FFT) architectures Digital system design High-speed FPGA design		Eric Work MS ECE, Sept. 2007 Software Engineer Soft Machines Arbitrary task to 2D mesh mapping Software tool flow CAD tools
	Wayne Cheng MS ECE, January 2008 ASIC Design Engineer Uniquify Dynamic voltage supply circuits Dynamic voltage and frequency circuits Transistor-level power simulations		Gouri Landge MS ECE, December 2009 Intel, Digital Home Group Video motion estimation architectures VLSI 65 nm motion estimation accelerator Programmable video processing hardware
	Stephen Le MS ECE, March 2010 Component Design Engineer Architecture Simulation Intel, Visual Computing Group Parallel H.264 application development High-speed parallel simulator Tool integration		Jeremy Webb MS ECE, March 2011 Engineer Keysight Division High-speed board design Many-core VLSI System interfacing
	Lucas Stillmaker MS ECE, September 2011 Graphics Hardware Engineer Intel, Visual and Parallel Computing Group (VPG) Intel Architecture Group (IAG) Parallel application development Parallel database sorting algorithms Digital system design		Trevin Murakami MS ECE, December 2011 Product Engineer NAND Solutions Group (NSG) Intel Many-core simulator Processor architectures Digital signal processing hardware
	Houshmand Shirani Mehr MS ECE, June 2012 Media encoder design, Component Design Engineer. Intel, Visual and Parallel Computing Group (VPG HW) Media Group Digital signal processing hardware Low Density Parity Check (LDPC) Decoders LDPC Algorithms		Nima Mostafavi MS ECE, June 2014 Hardware Engineer Microelectronics Group Oracle Hardware design DSP applications Software tools
	Michael Braly MS ECE, December 2015 Product Engineer New Product Introduction Altera Motion estimation engines Video compression Processor architectures		Emmanuel Adeagbo MS ECE, February 2017 Physical Design Engineer Big Core, Platform Engineering Group (PEG) Intel Regular expression applications Many-core tools VLSI Design
	Peiyao Shi MS ECE, October 2018 Product Development Engineer NAND Solutions Group (NSG) Intel Sparse matrix vector engines Many-core linear algebra engines System Design		Filipe Borges MS ECE, September 2019 Silicon Engineering Group Intel DSP applications Custom processor design Application design
	Christi Tain MS ECE, September 2019 Hardware Validation Engineer Storage Group Marvell CMOS chip design Place & route optimization Processor architecture		Renjie Chen MS ECE, September 2019 Moffett AI Wireless architectures DSP algorithms Digital architectures
	Arthur Hlaing MS ECE, March 2020 Microsoft LSTM Applications 3D processor mapping CAD tool development		Zhangfan Zhao MS ECE, February 2021 Nvidia Digital design Matrix inversion Hardware design
	Sharmila Kulkarni MS ECE, March 2021 Intel Arithmetic coding H.264 CABAC Digital system design		Yikai Mao MS ECE, September 2021 Ph.D. student, Keio University YOLO neural network Many-core application design Convolutional neural networks
	Haotian Wu MS ECE, December 2021 MediaTek RTL Design Engineer Residual neural nets Digital design Neural net architectures		Tony (Wai Cheong) Tsoi MS ECE, May 2022 Qualcomm Engineer Software-defined radio Automated test design RF interfaces
	Christian Lum MS ECE, June 2022 Northrop Grumman Payload System Engineering Digital System Design Hardware Neural Networks Radio Algorithms		Benjamin Moore MS ECE, June 2022 Keysight R&D Engineer, FPGA/DSP Software-defined radio Radio algorithms RF circuits
	Ziyuan Dong MS ECE, August 2022 Intel CG Product Development Engineer SqueezeNet Neural Net Architectures Hardware design		Aidan Callahan MS ECE, November 2022 AMD Product Development Engineer Video compression architectures H.264 Hardware design
	Thomas Abbott MS ECE, July 2023 Intel Image compression Parallel algorithms Digital architectures		Santhosh Sammeta MS ECE, September 2023 FPGA design PCIe interfaces Test strategies
	Jin Cui MS ECE, December 2023 SOI body-bias circuits Processor circuit architectures Intelligent optimization circuits		Yuxuan Huo MS ECE, January 2024 Numerical algorithms Transcendental functions Arithmetic optimization
Undergraduate Researchers
	Henna Huang BS ECE, June 2009 Ph.D. Student MIT Parallel H.264 application development Multi-processor characterization Tool development		Gary Chung BS ECE, August 2009 Apple Computer Embedded processor code development File system design and implementation Config design of 334-processor system
	Brian Zimmer BS ECE, June 2010 Ph.D. Student UC Berkeley MP3 decoder reference design MP3 decoder implementation		Layne Miao BS ECE, June 2011 Analog Design Engineer Intel Corporation AsAP2 board bring up System characterization
	Victoria Harvey BS ECE, June 2012 Ph.D. Student Stanford Many-core simulation Application development		Jonathan Earl BS ECE, June 2015 Maxim Integrated Motion estimation Video processing Many-core application development
	Dylan Finch BS ECE, June 2017 Redpine Signals MP3 parallelization Parallel application development Audio processing methods		Delvin Huynh BS ECE, June 2018 Apple Software-defined radios Many-core radios Laboratory SDR hardware
	Sarvagya Singh BS ECE, March 2018 Autonomous Driving Intern Xpeng Motors Many-core visualization CAD tool development Parallel application development		Yuanyuan Xiang BS ECE, June 2018 MS Student UCLA Many-core arithmetic Floating-point algorithms Fast division
	Hangyu Meng (Summer 2018) Zhejiang University Digital design HW architectures Hardware design		Ruochen Jiao (Summer 2018) Zhejiang University Digital design HW architectures Hardware design
	Ryan Atkins DRAM interface design FPGA development Hardware design		Jiayu Wang Software-defined radio Digital design Radio algorithms
	Ryan Ma Squeezenet architecture Convolutional neural nets FPGA design
William Au Yeung,   BS ECE, June 2005 Tomoko Tsuruta,   BS ECE, June 2005 Jason Cheung,   BS CS, June 2005 Leo Chan,   BS ECE, June 2006 Bassem Saad,   BS ECE, June 2006 Daniel Gurman,   BS ECE, June 2006 Sam Lee,   BS ECE, June 2006 Chi Chen,   BS ECE, June 2006 Kyle Piper,   BS ECE, June 2007

Programmable fine-grain many-core architectures and circuits.

Computationally-intensive application development.

Programming tool development such as compilers, optimization, and mapping tools.

Complete deep-submicron CMOS chip designs.

Asynchronous Array of simple Processors (AsAP)

Many members of the VCL are participating in work on the circuits, functional units, architecture, interconnection network, algorithms, applications, and tools for a high-performance and energy-efficient processing system targeting computationally-demanding multi-algorithm DSP system applications. The single-chip processing system is comprised of a large number of fine-grain asynchronously-operating programmable processors connected by a reconfigurable 2-dimensional mesh network.
AsAP 1.  The 0.18 μm AsAP 1 chip contains 36 programmable processors, operates at over 610 MHz at 2.0 V, and is believed to be the second highest clock rate processor designed in any university. Details of the chip were presented in the Technology and Architecture Directions session at ISSCC in Feb. 2006. See the paper below.
Also see the EE Times article "Asynchronous array of processors chip presented at ISSCC 2006," February 9, 2006.
AsAP 2.  A second generation 65 nm CMOS design contains 167 processors with dedicated FFT, Viterbi, and video motion estimation processors; 16 KB shared memories; and long-distance inter-processor interconnect. The programmable processors can individually and dynamically change their supply voltage and clock frequency. The chip is fully-functional. Processors operate up to 1.2 GHz at 1.3 V which is believed to be the highest clock rate fabricated processor designed in any university. At 1.2 V, they operate at 1.07 GHz and 47 mW when 100% active. At 0.675 V, they operate at 66 MHz and 608 μW when 100% active. This operating point enables 1 trillion MAC or ALU ops/sec with a power dissipation of only 9.2 Watts. Due to its MIMD architecture and fine-grain clock oscillator stalling, this energy efficiency per operation is almost perfectly constant across widely varying workloads--which is not the case for many architectures.

The 1000-processor KiloCore architecture and chip is the third generation fine-grain many-core processor array developed by members of the VCL.

A fourth-generation fabricated chip with significantly increased performance has been fabricated but not yet fully tested or published.

Low Density Parity Check (LDPC) Decoders

We are working on LDPC algorithms, architectures, and circuits targeting several regimes, with a continual emphasis on high energy efficiency:
• Very high rate decoders
• Efficient decoding algorithms useful at many throughput rates

Special Purpose Processors

We are working on algorithms, architectures, and circuits for a number of dedicated purpose processing engines. Several active projects include:
• Fast Fourier Transform (FFT)
• Viterbi decoder
• H.264 and HEVC video encoding and decoding
• second generation video motion estimation and stabilization
• database record processing
• other accelerator architectures



Sponsors of Our Work

	National Science Foundation   • CCF Grant No. 1321163   • CCF Grant No. 1018972   • REU Grant 2010   • CCF Grant No. 0903549   • CAREER award No. 0546907   • REU Grant 2005   • CCF Grant No. 0430090   • CCF Grant No. 0312837 (Co-PI)		SRC, Semiconductor Research Corporation   • GRC Grant 2321.001   • GRC Grant 1971.001   • CSR Grant 1659.001   • GRC Grant 1598.001
	ST Microelectronics		UC MICRO
	C2S2   • Grant 2047.002.014		Intellasys Corporation
	Intel Corporation	SEM	SEM
	Committee on Research, Faculty Research Grant		Fudan University
	Xilinx Incorporated, Equipment grants		Atheros Communications, Equipment grant
We also acknowledge support from:   • Artisan   • MOSIS
Any opinions, findings and conclusions or recomendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation (NSF).
The authors acknowledge the support of the C2S2 Focus Center, one of six research centers funded under the Focus Center Research Program (FCRP), a Semiconductor Research Corporation entity.

Publications

Publications in review are provided to sponsors but not yet listed here.


2023


• Santhosh Sammeta,
  "Characterization of a PCIe interface for a Many-Core chip Test Station,"
  Masters Thesis Plan II, VLSI Computation Laboratory, ECE Department, University of California, Davis, September 2023.

• Thomas Abbott and Bevan M. Baas,
  "A Scalable JPEG Encoder on a Many-Core Array,"
  IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapore, December 2023.
  In press.

• Shifu Wu and Bevan Baas,
  “Many-Core Display Stream Compression Decoders With Simplified Pixel Prediction,”
  IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Phoenix, Arizona, August 2023.

• Thomas Abbott,
  "JPEG Encoding on Fine-Grain Manycore Platforms,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, July 2023.

  2022
  

• Satyabrata Sarangi and Bevan M. Baas,
  "Energy-Efficient Canonical Huffman Decoders on Many-Core Processor Arrays and FPGAs,"
  Elsevier, Integration the VLSI Journal,
  In press.

• Peiyao Shi, Aaron Stillmaker, and Bevan M. Baas,
  "Efficient and High-Performance Sparse Matrix-Vector Multiplication on a Many-Core Array,"
  IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Penang, Malaysia, December 2022.

• Renjie Chen, Aaron Stillmaker, and Bevan M. Baas,
  "Architecture and 28 nm CMOS Design of a 1886 MBin/sec Context-Adaptive Binary Arithmetic Coder (CABAC) Encoder,"
  IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Patras, Greece, October 2022.

• Brent Bohnenstiehl, Aaron Stillmaker, Timothy Andreas, and Bevan M. Baas,
  "A Low-Overhead Method for the Accurate Estimation of the Maximum Operating Clock Frequency,"
  IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Patras, Greece, October 2022.

• Aidan Callahan,
  "H.264 Codec Implementation on a Many-Core Processor Array,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, November 2022.

• Ziyuan Dong,
  "An Energy-Efficient SqueezeNet Implementation on the KiloCore Platform,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, August 2022.

• Christian Lum,
  "Zero Crossing and Polar Discrimination Algorithms & Hardware for a Digital FM Receiver,"
  Masters Thesis Plan II, VLSI Computation Laboratory, ECE Department, University of California, Davis, June 2022.

• Benjamin Moore,
  "An All-Digital FM Reciever Implemented on the Xilinx ZCU111 RFSoC,"
  Masters Thesis Plan II, VLSI Computation Laboratory, ECE Department, University of California, Davis, June 2022.

• Tony (Wai Cheong) Tsoi,
  "Post-Silicon Hardware Validation of a Many-Core System,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, May 2022.

  2021
  

• Haotian Wu,
  "Residual Neural Network on a Many-Core Platform,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2021.

• Shifu Wu,
  "Design of Display Stream Compression Video Codecs,"
  Ph.D. Dissertation, VLSI Computation Laboratory, ECE Department, University of California, Davis, September 2021.

• Yikai Mao,
  "A Memory-Efficient YOLO Object Detection Convolutional Neural Network Inference Engine on the KiloCore 2 Manycore Platform,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, September 2021.

• Shifu Wu and Bevan M. Baas,
  "Display Stream Compression Decoders for Fine-Grained Many-Core Processor Arrays,"
  IEEE Transactions on Circuits & Systems II, May 2021.
  Invited.

• Satyabrata Sarangi and Bevan M. Baas,
  "DeepScaleTool: a Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era,"
  IEEE International Symposium on Circuits & Systems, Daegu, Korea, May 2021.

• Shifu Wu and Bevan M. Baas,
  "Display Stream Compression Decoders for Fine-Grained Many-Core Processor Arrays,"
  IEEE International Symposium on Circuits & Systems, Daegu, Korea, May, 2021.
  Received an invitation to an IEEE Transactions on Circuits and Systems II Special Issue.

• Zhangfan Zhao,
  "Matrix Inversion on a Many-Core Platform,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, March 2021.

• Sharmila Kulkarni,
  "Implementation of Context-Based Adaptive Binary Arithmetic Coding on KiloCore Processor Arrays,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, March 2021.

• Satyabrata Sarangi and Bevan M. Baas,
  "Canonical Huffman Decoder on Fine-grain Many-core Processor Arrays,"
  IEEE/ACM Asia and South Pacific Design Automation Conference, Tokyo, Japan, January, 2021.
  

  2020
  

• Shifu Wu and Bevan M. Baas,
  "Indexed Color History Many-Core Engines for Display Stream Compression Decoders,"
  IEEE International Conference on Electronics, Circuits & Systems, Glasgow, Scotland, November, 2020.
  

• Tokunbo Ogunfunmi, John McAllister, Bevan Baas and Mrityunjoy Chakraborty,
  "Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop,"
  Journal of Signal Processing Systems, August 2020.

• Aaron Stillmaker, Brent Bohnenstiehl, Lucas Stillmaker, and Bevan Baas,
  "Scalable Energy-Efficient Parallel Sorting on a Fine-Grained Many-Core Processor Array,"
  Journal of Parallel and Distributed Computing, vol. 138, pp. 32–47, April 2020.

• Daniel Kuzmenko, Carlos Feres, Timothy Andreas, Bevan Baas, Zhi Ding, Xiaoguang Liu, Harris Moyer, Ara Kurdoghlian, Hasan Sharifi,
  "Noncoherent Plug-and-Play RF Front-End Module for High Gain Spread Spectrum Communications and Interference Rejection,"
  Government Microcircuit Applications & Critical Technology Conference (GOMACTech), San Diego, CA, March 2020.

• Arthur Hlaing,
  "Long Short-Term Memory on a Many-Core Platform,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, March 2020.

• Brent Bohnenstiehl,
  "Design and Programming of the KiloCore Processor Arrays,"
  Ph.D. Dissertation, VLSI Computation Laboratory, ECE Department, University of California, Davis, March 2020.
  2019
  

• Renjie Chen,
  "Architecture and Hardware for a 1 Bin per Cycle Context-Adaptive Binary Arithmetic Coder (CABAC) Encoder,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, September 2019.

• Christi Tain,
  "Back-end Physical Design Flow for 28 nm FDSOI with Body-Bias,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, September 2019.

• Filipe Borges,
  "AlexNet Deep Neural Network on a Many Core Platform,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, September 2019.

  2018
  
• Peiyao Shi,
  "Sparse Matrix Multiplication on a Many-Core Platform,"
  Masters Thesis, Technical Report ECE-VCL-2018-1, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2018.

• Shifu Wu, Snehlata Gutgutia, Massimo Alioto and Bevan Baas,
  “Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding,”
  IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC), Pacific Grove, CA, October 2018.

• Bevan Baas, Brent Bohnenstiehl, and Jin Cui,
  “Exploration of Fine-Grain Body Bias Control in Many-Core Processor Arrays,”
  IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Burlingame, CA, October 2018.
  Invited.

• Shifu Wu and Bevan Baas,
  “A Low-Cost Slice Interleaving DSC Decoder Architecture for Real-Time 8K Video Decoding,”
  IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Windsor, ON, Canada, August 2018.
  2017
  
• Jon Pimentel,
  "Methods for Reducing Floating-Point Computation Overhead,"
  Ph.D. Dissertation, Technical Report ECE-VCL-2017-2, VLSI Computation Laboratory, ECE Department, University of California, Davis, August 2017.

• Michael Braly, Aaron Stillmaker and Bevan Baas,
  "A Configurable H.265-Compatible Motion Estimation Accelerator Architecture for Realtime 4K Video Encoding in 65nm CMOS,"
  In Proceedings of the IEEE Conference on Dependable and Secure Computing, Taipei, Taiwan, August 2017.

• Aaron Stillmaker, Brent Bohnenstiehl and Bevan Baas,
  "The Design of the KiloCore Chip,"
  ACM/IEEE Design Automation Conference, (DAC), Austin, TX, June 2017.
  Invited.

• Aaron Stillmaker and Bevan Baas,
  "Scaling Equations for the Accurate Prediction of CMOS Device Performance from 180 nm to 7 nm,"
  Integration, the VLSI Journal, vol. 58, pp. 74–81, June 2017.
  

• Brent Bohnenstiehl, Aaron Stillmaker, Jon Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo and Bevan Baas,
  "KiloCore: A 32 nm 1000-Processor Computational Array,"
  IEEE Journal of Solid-State Circuits (JSSC), vol. 52, no. 4, pp. 891–902, April 2017.
  Invited.

• Brent Bohnenstiehl, Aaron Stillmaker, Jon Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo and Bevan Baas,
  "KiloCore: A Fine-Grained 1000 Processor Array for Task Parallel Applications,"
  IEEE Micro, vol.37, no.2, pp. 63-69, March-April 2017.
  Invited.

• Emmanuel O. Adeagbo,
  "Energy-Efficient Pattern Matching Methods on a Fine-Grained Many-Core Platform,"
  Masters Thesis, Technical Report ECE-VCL-2017-1, VLSI Computation Laboratory, ECE Department, University of California, Davis, March 2017.
  2016
  
• Bin Liu,
  "Energy-Efficient Computing with Fine-grained Many-Core Systems,"
  Ph.D. Dissertation, Technical Report ECE-VCL-2016-1, VLSI Computation Laboratory, ECE Department, University of California, Davis, September 2016.

• Brent Bohnenstiehl, Aaron Stillmaker, Jon Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo and Bevan Baas,
  "KiloCore: A 32 nm 1000-Processor Array,"
  In Proceedings of the IEEE HotChips Symposium on High-Performance Chips (HotChips 2016), Cupertino, CA, August 2016.
  Received an invitation to an IEEE Micro Special Issue.

• Jon Pimentel, Brent Bohnenstiehl and Bevan Baas,
  "Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs,"
  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 25, no. 1, pp. 100-113, January 2017. (Official date of publication July 12, 2016).

• Brent Bohnenstiehl, Aaron Stillmaker, Jon Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo and Bevan Baas,
  "A 5.8 pJ/Op 115 Billion Ops/sec, to 1.78 Trillion Ops/sec 32 nm 1000-Processor Array,"
  Symposium on VLSI Circuits, Honolulu, HI, June 2016.
  Received an invitation to an IEEE Journal of Solid-State Circuits (JSSC) Special Issue.
  2015
  
• Aaron Stillmaker,
  "Design of Energy-Efficient Many-Core MIMD GALS Processor Arrays in the 1000-Processor Era,"
  Ph.D. Dissertation, Technical Report ECE-VCL-2015-1, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2015.

• Michael Braly,
  "A Configurable H.265-Compatible Motion Estimation Accelerator Architecture Suitable for Realtime 4K Video Encoding,"
  Masters Thesis, Technical Report ECE-VCL-2015-2, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2015.

• Jon Pimentel, Aaron Stillmaker, Brent Bohnenstiehl and Bevan Baas,
  "Area Efficient Backprojection Computation with Reduced Floating-Point Word Width for SAR Image Formation,"
  IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC), Pacific Grove, CA, November 2015.
  

• Brent Bohnenstiehl and Bevan Baas,
  "A Software LDPC Decoder Implemented on a Many-Core Array of Programmable Processors,"
  IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC), Pacific Grove, CA, November 2015.
  

• Emmanuel O. Adeagbo and Bevan Baas,
  "Energy-Efficient String Search Architectures on a Fine-Grained Many-Core Platform,"
  Technology and Talent for the 21st Century (TECHCON 2015), Austin, TX, September 2015.

• Bin Liu, Mohammad H. Foroozannejad, Soheil Ghiasi and Bevan Baas,
  "Optimizing Power of Many-Core Systems by Exploiting Dynamic Voltage, Frequency and Core Scaling,"
  IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, CO, August 2015.
  Best Student Paper Award, Third Place.
  2014
  
• Jon Pimentel and Bevan Baas,
  "Hybrid Floating-Point Modules with Low Area Overhead on a Fine-Grained Processing Core,"
  IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC), Pacific Grove, CA, November 2014.
  Best Student Paper Award, Third Place.

• Bin Liu, Brent Bohnenstiehl and Bevan Baas,
  "Scalable Hardware-Based Power Management for Many-Core Systems,"
  IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC), Pacific Grove, CA, November 2014.
  

• Jon Pimentel and Bevan Baas,
  "Software/Hardware Hybrid Floating-Point Units with Low Area Overhead on a Fine-Grained Processing Core,"
  Technology and Talent for the 21st Century (TECHCON 2014), Austin, TX, September 2014.

• Nima Mostafavi,
  "Hardware, Software, and Tools for an AsAP2 Many-Core System,"
  Masters Thesis, Technical Report ECE-VCL-2014-1, VLSI Computation Laboratory, ECE Department, University of California, Davis, June 2014.

• Mohammad H. Foroozannejad, Matin Hashemi, Alireza Mahini, Bevan Baas and Soheil Ghiasi,
  "Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms,"
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, no. 5, pp. 752-762, May 2014.
  2013
  
• Zhibin Xiao and Bevan Baas,
  "A Hexagonal Processor and Interconnect Topology for Many-core Architecture with Dense On-Chip Networks,"
  Book Chapter in IFIP Advances in Information and Communication Technology, Springer, 2013.
  Invited.

• Aaron Stillmaker, Lucas Stillmaker, Brent Bohnenstiehl and Bevan M. Baas,
  "Energy-Efficient Sorting on a Many-Core Platform,"
  Technology and Talent for the 21st Century (TECHCON 2013), Austin, TX, September 2013.

• Anh Tran and Bevan Baas,
  "Achieving High-Performance On-Chip Networks with Shared-Buffer Routers,"
  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 22, no. 6, pp. 1391-1403, June 2014. (Official date of publication July 3, 2013.)

• Zhibin Xiao and Bevan Baas,
  "Processor Tile Shapes and Interconnect Topology for Dense On-Chip Networks,"
  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 22, no. 6, pp. 1377-1390, June 2014. (Official date of publication June 25, 2013.)

• Bin Liu and Bevan Baas,
  "Parallel AES Encryption Engines for Many-Core Processor Arrays,"
  IEEE Transactions on Computers, vol. 62, no. 3, pp. 536-547, March 2013.
  

• Rasit Topaloglu and Bevan Baas,
  "Guest Editors' Introduction to Practical Parallel EDA,"
  IEEE Design & Test, vol. 30, Issue 1, February 2013.
  

• Tinoosh Mohsenin, Houshmand Shirani-Mehr and Bevan Baas,
  "LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization,"
  VLSI Design, vol. 2013, 14 pages, February 2013.
  
  2012
  
• Zhibin Xiao,
  "Energy-efficient Fine-grained Many-core Architecture for Video and DSP Applications,"
  Ph.D. Dissertation, Technical Report ECE-VCL-2012-4, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2012.

• Aaron Stillmaker, Lucas Stillmaker and Bevan M. Baas,
  "Fine-Grained Energy-Efficient Sorting on a Many-Core Processor Array."
  IEEE International Conference on Parallel and Distributed Systems (ICPADS 2012), Singapore, December 2012

• Zhibin Xiao and Bevan Baas,
  "A Hexagonal Shaped Processor and Interconnect Topology for Tightly-tiled Many-core Architecture,"
  IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) , Santa Cruz, CA, Oct. 2012.
  Received an invitation to a Book Chapter.

• Anh Tran,
  "On-Chip Network Designs for Many-Core Computational Platforms,"
  Ph.D. Dissertation, Technical Report ECE-VCL-2012-3, VLSI Computation Laboratory, ECE Department, University of California, Davis, August 2012.
  UC Davis College of Engineering 2013 Zuhair A. Munir Award for Best Doctoral Dissertation, Honorable Mention

• Anh Tran and Bevan Baas,
  "NoCTweak: a Highly Parameterizable Simulator for Early Exploration of Performance and Energy of Networks On-Chip,"
  Technical Report ECE-VCL-2012-2, VLSI Computation Laboratory, ECE Department, University of California, Davis, July 2012.

• Houshmand Shirani-Mehr,
  "A Reduced Routing Network Architecture for Partial Parallel LDPC Decoders,"
  Masters Thesis, Technical Report ECE-VCL-2012-1, VLSI Computation Laboratory, ECE Department, University of California, Davis, June 2012.

• Bin Liu and Bevan Baas,
  "Energy-Efficient AES Ciphers on a Fine-Grained Many-Core System ,"
  Technology and Talent for the 21st Century (TECHCON 2012), Austin, TX, Sep. 2012
  

• Allen Baum and Bevan Baas,
  "Introduction to the Special Issue: Hot Chips 23,"
  IEEE Micro, Volume 32, Number 2, March/April 2012.

• Zhibin Xiao and Bevan Baas,
  "Processor Shapes and Topologies for Dense On-chip Networks,"
  presented in the IEEE International Solid-Sate Circuit Conference (ISSCC 2012) student forum, San Francisco, CA, Feb. 2012.

Bevan M. Baas,
"A Pipelined Memory System For an Interleaved Processor,"
Technical Report NSF-GF-1992-1, STARLab, EE Department, Stanford University, June 1992.

In The News

• KiloCore 1000-processor chip
  • Reported in publications such as: Ars Technica, Daily Mail, Digital Journal, EE Times, Electronics Weekly, Engadget, Enterprise Tech, ExtremeTech, Financial Express, Gadget Mash, Inquirer, Mashable, Motherboard, NDTV, Next Big Future, NSF Science 360 Video News, PC Magazine, PC Review, PC World, The Register, Science Daily, SlashGear, Tech Switch, Tech Times, The Next Platform, The Verge, Wired, ZDNet, and more than 100 others...

• New 167-processor chip is super-fast, ultra energy-efficient
  • EurekAlert news service operated by AAAS TechRadar, UC Davis News Service, and many others.

Projects for Interested Graduate Students

• New scalable algorithms, layouts, and mappings for Scientific kernels such as matrix multiplication, sparse matrix operations, inversion, and others

• New scalable algorithms, layouts, and mappings for Machine learning applications

• Processor simulation, emulation, and CAD design flow

• Code scheduler programming tool (update to new architecture and new capabilities)

• General domain: Programmable DSP processor design

• General domain: Parallel DSP algorithms

• General domain: Reconfigurable inter-processor networks for various network traffic styles

• General domain: Functional unit and circuit design

• Development of our C compiler for our many-core processor arrays

• Arbitrary graph mapping algorithms and tools

• Dynamic supply voltage and clock frequency circuits and algorithms

• Shorter-term projects (for undergraduate, MS, or Ph.D. starter projects)
  • Measurement and characterization of our multi-core chips (longer term)
  • System-level applications utilizing our AsAP2 + workstation + FPGA platform
  • I/O delay auto-calibration for our AsAP2 + workstation + FPGA platform
  • Second generation FFT accelerator processor
  • FPGA implementations of Wi-Fi, H.264, FFT, AES, and other applications
    Compare fpgas/many-core commercial/own-design: programming tools, layout area, energy for functions
  • Full H.264 encoder and decoder on AsAP array
  • Various FFTs on AsAP array
  • Chip design CAD tool projects
  • Arbitrary graph drawing program
  • Quick: bibtex processing script (authors)
  • Quick: dircmp (script to recursively diff directories of files)

• A note to interested prospective students

Downloadable Tools Developed in the VCL

• NoCTweak: a Highly Parameterizable Networks-On-Chip Simulator
  
  
• Arbitrary Graph to 2D Mesh Mapping Tool    
  
  
• Low overhead parallel-task linux based simulator    
  
  
• Dual-clock FIFO    
  
  

VCL Laboratory Information

• Directions to the VCL lab

• Some VCL Guidelines for students in the VCL lab (good computer etiquette, writing papers, responding to reviewers)

• Unix command notes, Unix tutorials, LaTeX notes

• Information on the FPGA boards used in the lab

• Getting started in the VCL lab

Laboratory Resources

In addition to significant computing resources, the VCL owns a large number of electronic test and measurement instruments. These include the following Agilent and Tektronix instruments:
• TLA7012 Logic Analyzer with
  • 7PG2 64-channel pattern generator module 1M/channel memory and
  • 7AA2 68-channel logic analyzer 512K/channel memory,
• TDS7154B 4-channel 20 GSample/sec 1.5 GHz 4M/channel memory oscilloscope,
• 54831D 4+16-channel 4 GSample/sec 600 MHz oscilloscope,
• TDS5034B 4-channel 350 MHz oscilloscope,
• 81130A 660 MHz pulse generator,
• AFG3252 2 GSample/sec 120 MHz Arbitrary Waveform Generator,
• (5) 6611C, 6611C, and 6631B Precision Power Supplies,
• (11) E3642A, E3644A, E3633A, E3610A power supplies, and
• a wide variety of multimeters, probes and other equipment and supplies.
Virtually all instruments are GPIB (IEEE 488)-controllable and are connected to the laboratory's instrumentation control network. In addition to the group's instruments, through a sharing agreement with other groups in the Kemper 2201 laboratory, we have access to a vast array of other test and measurement equipment.

General Informative Web Pages

• Many-Core Fabricated Chips Information Page

• Fabricated Programmable Processors Designed in Academia Information Page

• Fabricated SIMD Processors Information Page

• General Purpose Desktop GPU Information Page

• VLSI & Sig. Processing conferences, Our favorite conferences,
  Our favorite conferences II
  Digital VLSI Conferences, Chalmers

Some of the CAD and Other Tools We Use

• Some tools installed locally
• Cadence
  • Tool notes
  • NC verilog
  • SoC Encounter
  • Virtuoso
• Synopsys
  • Design Compiler
  • HSpice
  • NanoSim
• Mentor Graphics
  • Calibre
  • Expedition
• Magic layout tool
  • Magic web site
• LaTeX
  • Notes for LaTeX on Windows, v1.0
• Tutorial web pages
  • Cadence, NCSU, and various tutorials

Other Useful Links

• IEEE papers
  • JSSC
  • TVLSI
  • TCAS I: Regular papers;
  Publication statistics
  • TCAS II: Express briefs
• Intl. Tech. Roadmap for Semiconductors (ITRS)
• MOSIS web site
• Future technology spice decks from UCB's Predictive Technology Model
• Accurel for FIBing, packaging,...
• AsAP Wikipedia page
• gds2pov, a 3D GDSII visualization tool

Informative References

• LaTeX: Formulas,
• Deep chip's CAD tool review from CAD '04

A few group pictures

Alumni: Eric Work, Dr. Zhibin Xiao, Wayne Cheng, Bevan Baas, Mike Lai, Michael Braly at ECExpo, Santa Clara, Feb 26, 2020.

Tim, Brent, Prof. Zhiyi Yu, Prof. Aaron Stillmaker, Shifu, Bevan, Satyabrata, Dr. Anh Tran, Prof. Tinoosh Mohsenin, Dr. Zhibin Xiao at ISSCC, Feb 18, 2019.

Sharmila, Tim, Yushan, Felipe, Yuanyuan, Renjie, Bevan, Sarvagya, Shifu, Satyabrata, Jin, Mark at graduation ice-cream celebration; June 14, 2018.

Yushan, Yuanyuan, Sharmila; June 14, 2018.

Tim, Satyabrata, Jon, and Shifu at Jon's graduation ceremony; June 15, 2017.

Shifu, Satyabrata, Emmanuel, Aaron, and Lucas at Aaron and Emmanuel's graduation ceremony; June 9, 2016.

Brent, Aaron, Jon, and Emmanuel finishing up the KiloCore2 tapeout; March 1, 2015.

Lucas, Aaron, Bevan, Zhibin, Jon, and Anh at Zhibin and Lucas' graduation ceremony; June 14, 2012.

Aaron, Michael, Emmanuel, Jon, Anh, Samir, Zhibin, Brent, and Bin in the office-lab; April 4, 2012.

Group dinner celebrating Jeremy, Lucas, and Trevin's graduations as well as Anh's best paper award and Bin's best paper nomination; January 25, 2012.

Group lunch celebrating end of Spring quarter; June 10, 2009.

Dean and Anh in office-lab; January 25, 2009.

Dean, Zhibin and Paul in office-lab; March 27, 2008.

Zhibin, Dean, Anh, Tinoosh, and Paul working on AsAP2 bringup; October 12, 2007.

Tinoosh, Dean, and Zhibin working on AsAP2 bringup; October 11, 2007.

Dean, Zhibin, Anh, Tinoosh, Paul, and Bevan at ECE Grad Student BBQ in Kemper courtyard; October 4, 2007.

Toney, Wayne, Zhibin, Anh, Zhiyi, Tinoosh, Paul, Dean, and Bevan celebrating Toney's and Wayne's graduations at Woodstock's; August 29, 2007.

Tinoosh, Dean, Christine, Wayne, and Zhiyi in Kemper 2211; November 8, 2006.

Ryan, Omar, Mike M., Zhiyi, Mike L., and Bevan near the quad after lunch; August 26, 2004.

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ECE Dept. | UC Davis

Last update: October 30, 2019
Keywords: many-core, multi-core, array processor, homogenous, heterogeneous, NoC, network on chip, interconnect, mesh, GALS, globally asynchronous locally synchronous, electrical engineering, computer engineering, university, academic, department, group, lab, laboratory, research development, chip, VLSI, CMOS, circuit, ASIC, FPGA, low power, energy efficient, FFT, DCT, viterbi, FIR, IIR, compression, communication, coding, convolution, correlation, encryption, image, video, JPEG, multimedia, wireless, OFDM, radar, sonor, medical imaging, MRI, magnetic resonance imaging, biological imaging, 802.11a, 802.11g, wireless LAN, transmitter, receiver, H.264 video compresssion encoding decoding, encoder decoder, codec, AES encryption decryption, networks on-chip, on-chip networks, routers, source-synchronous, interconnects, interconnection