Techniques for reducing both dynamic and leakage power of a single-chip multiprocessor while minimizing area and performance overhead are examined within this thesis. Variations in the workload across processors allow for reducing the supply voltage and clock frequency to save power. The design decisions are arrived by thorough investigations into the tradeoffs between various ideas, both from the author and from other experiments. A dynamic voltage and frequency scaling (DVFS) circuit is designed as a wrapper to the AsAP (Asynchronous Array of Simple Processors) processor core. Dynamic power reduction is accomplished through voltage scaling across two voltage supplies with PMOS power gates. Shutting the power gates off for unused processors provides additional leakage power savings. Adding additional power gates in parallel and decoupling capacitors help to combat the performance overhead of using power gates. A complex supply switching logic design ensures proper operation through processor stall signals, and guards against shorting the supplies and excessive power grid noise. Workload is determined by the utilization of the processor's input FIFOs, and analysis is performed by a configurable FIR/IIR filter. The clock frequency and supply voltage are scaled dynamically based on the workload. The highly configurable interface of the dynamic voltage and frequency scaling circuit allows for enough flexibility to handle the various applications that an AsAP processor can support. Results show significant reductions in dynamic power and energy with relatively small area and performance overhead. The design is implemented on an AsAP architecture with an 11.5% area overhead. On a 9 processor JPEG application with two voltage supplies of 1.3 V and 0.8 V, running with DVFS resulted in an average of almost half of original energy consumption (52%), with an 8% performance overhead. The average relative energy delay product was 56%.
Wayne H. Cheng, "Approaches and Designs of Dynamic Voltage and Frequency Scaling," Technical Report ECE-CE-2008-1, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2008.
@mastersthesis{whcheng:msthesis,
author = {Wayne H. Cheng},
title = {Approaches and Designs of Dynamic Voltage and Frequency
Scaling},
school = {University of California},
year = 2008,
address = {Davis, CA, USA},
month = Jan,
note = {\url{http://www.ece.ucdavis.edu/vcl/pubs/theses/2008-1}}
}