Architecture and Hardware for a 1 Bin per Cycle Context-Adaptive Binary Arithmetic Coder (CABAC) Encoder

Renjie Chen
Masters Thesis
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis
VLSI Computation Laboratory, University of California, Davis, 2019.

Abstract

Entropy encoding is a key element in H.264/MPEG-4 AVC video coding responsible for the lossless compression of transformed and quantized data. Context-Adaptive Binary Arithmetic Coding (CABAC) is one of the two entropy coding methods available in the H.264 standard. CABAC achieves its high compression ratios by combining arithmetic coding with adaptive context modeling. Compared to the other entropy coding method which is called Context-Adaptive Variable-Length Coding (CAVLC), CABAC achieves a 15% to 19% greater bit-rate reduction. However, the computational complexity of CABAC is much greater than the complexity of CAVLC, so hardware acceleration for CABAC is necessary for real-time high resolution video coding.

This thesis presents a hardware CABAC encoder implementation for the H.264 main profile. The implementation supports all CABAC functions including context initialization, binarization, context modeling and binary arithmetic coding in hardware. The architecture of the CABAC encoder consists of six pipeline stages and is capable of encoding at a rate of 1 bin per cycle where a bin is a binarized symbol encoded in arithmetic coding. In functional simulation, the output generated from the presented CABAC encoder is perfectly matched with the output of the CABAC module in H.264 JM reference software. The CABAC encoder was implemented in a 28 nm FD-SOI CMOS technology and it achieves a throughput of 769 million bins per second which is sufficient to encode real-time 4K UHD (3840×2160) video at 60 frames per second while dissipating an average power of 11.48 mW. The circuit area is 33,411 μm² which is a logic gate count of 23.4K equivalent minimum NAND gates.

Thesis

  PDF (9.8 MB),   (c) Copyright, 2019

Reference

Renjie Chen, "Architecture and Hardware for a 1 Bin per Cycle Context-Adaptive Binary Arithmetic Coder (CABAC) Encoder," Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2019.

BibTeX entry

@mastersthesis{peiyao:vcl:mastersthesis,
   author      = {Renjie Chen},
   title       = {Architecture and Hardware for a 1 Bin per Cycle Context-Adaptive Binary Arithmetic Coder ({CABAC}) Encoder},
   school      = {University of California, Davis},
   year        = 2019,
   month       = dec,
   address     = {CA, USA},
   note        = {\url{http://vcl.ece.ucdavis.edu/pubs/theses/2019-3.renjie/}}
   }