Hardware, Software, and Tools for an AsAP2 Many-Core System

Abstract:

This thesis describes the design and implementation of hardware and software which enable the integration of the 167-processor AsAP2 processor array chip into a system containing DRAM memory, mass storage, and high-speed interconnect. A new daughtercard utilizes high-speed LVDS interconnect for data and control interfaces between the array processor chip and a commercial FPGA board which serves as a hub for the entire system. Verilog code on the FPGA board automates programming of the AsAP2 chip using PCIe or JTAG connections and also enables the AsAP2 input and output data interfaces to communicate through a PCIe connection to the host computer. A scheduler program written in Perl reduces instruction counts and increases performance of AsAP2 assembly code by line re-arranging, register forwarding, and register renaming. Many Perl and C programs on the host computer simplify the conversion of the assembly programs and the input and output data in human readable format on the host computer to the machine code formats transferable to the FPGA board and vice versa. This interface design enables the design and implementation of many features such as SSD hard drives, DDR3 memories, and fiber optic networks that lead to the use of the low power AsAP2 chip in a large enterprise system.

Thesis

  PDF (13 MB),   (c) Copyright, 2014

Reference

Nima Mostafavi, "Hardware, Software, and Tools for an AsAP2 Many-Core System," Masters Thesis, Technical Report ECE-VCL-2014-1, VLSI Computation Laboratory, ECE Department, University of California, Davis, 2014.

BibTeX entry

@mastersthesis{nmostiv:msthesis,
   author      = {Nima Mostafavi},
   title       = {Hardware, Software, and Tools for an AsAP2 Many-Core System},
   school      = {University of California},
   year        = 2014,
   address     = {Davis, CA, USA},
   month       = jun,
   note        = {\url{http://vcl.ece.ucdavis.edu/pubs/theses/2014-1/}}
   }