A Reduced Routing Network Architecture for Partial Parallel LDPC Decoders

Abstract:

A novel partial parallel decoding scheme based on the matrix structure of LDPC codes proposed in IEEE 802.15.3c and IEEE 802.11ad standards is presented that significantly simplifies the routing network of the decoder, and the class of parity-check matrices for which the method can be used is defined. The proposed method results in an almost complete elimination of logic gates on the routing network, which yields improvements in area, speed and power, with an identical error correction performance to conventional partial-parallel decoders. A decoder for the (672,588) LDPC code adopted in the IEEE 802.11ad standard is implemented in a 65 nm CMOS technology including place & route with both proposed permutational decoder, and conventional partial-parallel architecture. The proposed permutational LDPC decoder operates at 235 MHz and delivers a throughput of 7.9 Gbps with 5 decoding iterations per block. Compared to a conventional partial-parallel decoder, the proposed decoder achieves a throughput 30% higher and at the same time requires a chip area approximately 24% smaller.

Paper

  PDF (1.54 MB),   (c) Copyright, 2012

Reference

Houshmand Shirani-Mehr, "A Reduced Routing Network Architecture for Partial Parallel LDPC Decoders" Technical Report ECE-VCL-2012-1, VLSI Computation Laboratory, ECE Department, University of California, Davis, 2012.

BibTeX entry

@mastersthesis{hshirani:msthesis,
   author      = {Houshmand Shirani-Mehr},
   title       = {A Reduced Routing Network Architecture for Partial Parallel LDPC Decoders},
   school      = {University of California},
   year        = 2012,
   address     = {Davis, CA, USA},
   month       = Jun,
   note        = {\url{http://www.ece.ucdavis.edu/vcl/pubs/theses/2012-1/}}
   }