Processor Tile Shapes and Interconnect Topology for Dense On-Chip Networks

VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

Abstract:

We propose two eight-neighbor, two five-nearest-neighbor, and three six-nearest-neighbor interconnection topologies for many-core processor arrays--three of which use five-sided or hexagonal processor tiles--which typically reduce application communication distance and result in an overall application processor that requires fewer cores and lower power consumption. A 16-bit processor with the appropriate number of input and output ports is implemented in all topologies and tile shapes. The hexagonal and five-sided processor tiles and arrays of tiles are laid out with industry standard automatic place and route design flow and Manhattan-style wires without full-custom layout. A 1080p H.264/AVC residual video encoder and a 54 Mb/s 802.11a/g OFDM wireless local area network baseband receiver are mapped onto all topologies. The six-neighbor hexagonal tile incurs a 2.9% area increase per tile compared with the four-neighbor 2-D mesh, but its much more effective interprocessor interconnect yields an average total application area reduction of 22% and an average application power savings of 17%.

Paper

PDF (3.1 MB)

Reference

Zhibin Xiao and Bevan M. Baas, "Processor Tile Shapes and Interconnect Topology for Dense On-Chip Networks," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 22, no. 6, pp. 1377–1390, June 2014. (Official date of publication June 25, 2013.)

Note on Publication Date

Although the official publication date of this paper is June 25, 2013, it did not appear in print until the June 2014 issue of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI).

"Manuscript received August 16, 2012; revised January 16, 2013 and March 18, 2013; accepted May 9, 2013. Date of publication June 25, 2013; date of current version May 20, 2014."

BibTeX Entry

@article{xiao:tvlsi:2013,
   author    = {Zhibin Xiao and Bevan M. Baas},
   title     = {Processor Tile Shapes and Interconnect Topology for Dense On-Chip Networks},
   journal   = {IEEE Transactions on Very Large Scale Integration Systems (TVLSI)},
   month     = jun,
   year      = 2014,
   volume    = 22,
   number    = 6,
   pages     = {1377--1390},
   note      = {Official date of publication June 25, 2013}
   }

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Last update: August 8, 2014