PDF (9.4 MB),
(c) Copyright, 2019
Christi Tain
Masters Thesis
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis
Technical Report ECE-VCL-2019-2,
VLSI Computation Laboratory,
University of California, Davis, 2019.
VLSI design consists of RTL coding, synthesis, place and route, and fabrication. Physical design describes the place and route process. Compared to front-end RTL and synthesis, back-end physical design involves wires with parasitic effects, clock trees with inverters and buffers, IR-affected power grids, and Multi-Mode Multi-Corner (MMMC) simulations. MMMC simulations analyze timing in various processes, voltages, and temperatures. As a result, practical timing and power of a circuit can only be fully analyzed and optimized through physical design.
This thesis presents a physical design flow used for 28 nm FDSOI technology with body bias. Body bias involves connecting the body of a transistor to a secondary power source. The inclusion of body bias adds a level of configuring when designing the power network. The methodologies for floorplanning, power, placement, clock tree synthesis, routing, and verification are examined. The optimization of timing and IR drop are also discussed. Issues encountered at each stage are explored and several solutions are proposed to solve these issues.
After the methodologies and optimizations are discussed, the final design flow is implemented using Cadence Innovus v19.10. Three design blocks are placed and routed. The smallest design block is a RGB to YCoCg synthesizer that converts a RGB pixel to a YCoCg format. The intermediate design block is a Context Adaptive Binary Arithmetic Coder (CABAC), which is an entropy coding scheme for H.264 main profile, high profile, and extended profile. The largest design block is a Display Stream Compression (DSC) decoder for 4K and 8K video decoding.
PDF (9.4 MB),
(c) Copyright, 2019Christi Tain, "Back-end Physical Design Flow for 28 nm FDSOI with Body-Bias," Masters Thesis, Technical Report ECE-VCL-2019-2, VLSI Computation Laboratory, ECE Department, University of California, Davis, September 2019.
@mastersthesis{ctain:vcl:mastersthesis,
author = {Christi Tain},
title = {Back-end Physical Design Flow for 28 nm FDSOI with Body-Bias},
school = {University of California, Davis},
year = 2019,
address = {CA, USA},
month = sep,
note = {\url{http://vcl.ece.ucdavis.edu/pubs/theses/2019-2.ctain/}}
}