This page contains one comprehensive table listing key attributes of fabricated SIMD (single instruction, multiple data) chips.It includes the chips that we could find but not it is not intended to be exhaustive.
The table is Sortable by clicking a column heading in the top row. Clicking once, the table will be sorted from low to high, and clicking twice, the table will be sorted from high to low.
| Year | Processor | SIMD Arrays | Proc Elements (total) |
Clock Rate (MHz) |
CMOS Tech (nm) |
Voltage (V) |
Die Area (mm^2) |
Power (W) |
Performance | Organization | Reference |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 1985 ? | CM-1 | 1 | 65536 | 4 | - | - | - | 12000 W@4MHz | 1000 MIPS | Thinking Machines Corporation | [8] |
| 1987 | CM-2 | 1 | 16384, 32768, or 65536 | - | - | - | - | 2800 W | 2500 MIPS; 28 GFLOPS | Thinking Machines Corporation | [9] |
| 1992 | CM-200 | 1? | 65536 (or 2K, 4K, 8K, 16K, 32K) | - | - | - | - | - | 40 GFLOPS | Thinking Machines Corporation | [9] |
| 1995 | Abacus | 1 | 1024 | 125 | 1000 | - | 95.04 | - | 2 GOPS | MIT | [10] |
| 2005 | T1P2000 | 5 | 25 | 668.25 | 90 | - | - | - | 55.5 GOPS | Telairity | [1] [2] [3] |
| 2006 | CA1024 | 1 | 1024 | 200 | 130 | - | - | - | >2GOPS/mm^2 | Connex | [4] |
| 2008 | CSX700 | 2 | 192 | 250 | 90 | 1 | - | 10 | 96GFLOPS @250MHz | ClearSpeed | [5] |
| 2011 | ePUMA | 4 ? | 32 | - | 65 | - | 23 | 4 ? | 100GOPS | Linköping University | [6] [7] |
| Year | Processor | SIMD Arrays | Proc Elements (total) |
Clock Rate (MHz) |
CMOS Tech (nm) |
Voltage (V) |
Die Area (mm^2) |
Power (W) |
Performance | Organization | Reference |
[1] Telairity-1:A New Processor Architecture for High-Definition Video, White Paper.
[2] http://www.bdti.com/InsideDSP/2005/08/15/Telairity.
[3] http://www.telairity.com/technology.html.
[4] Stefan, Gheorghe, et al. "The ca1024: A fully programable system-on-chip for cost-effective hdtv media processing." Hot Chips: A Symposium on High Performance Chips. 2006.
[5] http://www.clearspeed.com/products/csx700.php.
[6] Liu, Dake, et al. "ePUMA embedded parallel DSP processor with Unique Memory Access." Information, Communications and Signal Processing (ICICS) 2011 8th International Conference on. IEEE, 2011.
[7] Wang, Jian, Joar Sohl, and Dake Liu. "Architectural support for reducing parallel processing overhead in an embedded multiprocessor ." Embedded and Ubiquitous Computing (EUC), 2010 IEEE/IFIP 8th International Conference on. IEEE, 2010.
[8] William Daniel Hillis, PhD. dessertation, "The Connection Machine", MIT, June, 1985.
[9] "Thinking Machines Corporation", New-npac.org, 2016. [Online]. Available: http://www.new-npac.org/projects/cdroms/cewes-1999-06-vol1/nhse/hpccsurvey/orgs/tmc/tmc.html. [Accessed: 20- Jul- 2016].
[10] Bolotski, Michael, et al. "Abacus: a 1024 processor 8 ns SIMD array." Advanced Research in VLSI, 1995. Proceedings., Sixteenth Conference on. IEEE, 1995.
This page is maintained by members of the VLSI Computation Laboratory at UC Davis.
Last update: July 20, 2016