A SystemC Single-Cycle Simulator

Abstract:

Fine-grained multi-core systems such as the Asynchronous Array of Simple Processors can be described in different ways. Detailed hardware description language implementations, such as using Verilog, can provide a means of verifying the final fabricated chip, but are cumbersome to prototype changes, when shared provide no intellectual property security, and as the system grows more complex the simulator's performance degrades. Another option is to use statistical modeling of the system, but these are too imprecise for our goals and require careful characterization of the system. The alternative proposed here is to design a simulator of a simpler architecture and add features to emulate the functionality of the full processor. This work provides an example simulator using a simplified single-cycle processor model with some alterations to mimic the behavior of a pipelined processor. This simulator provides easy-to-alter functional representations of the inner workings, fast simulation speeds, and provides logs of key profiling information for application developers. It has been verified with bit-accurate outputs and 0.037-0.47% error in simulated time while potentially reducing the code size by 71% lines of code compared to a more detailed hardware description language implementation.

Paper

  PDF (861 KB),   (c) Copyright, 2011

Reference

Trevin Murakami, "A SystemC Single-Cycle Simulator" Technical Report ECE-VCL-2011-3, VLSI Computation Laboratory, ECE Department, University of California, Davis, 2011.

BibTeX entry

@mastersthesis{tmurakami:msthesis,
   author      = {Trevin Murakami},
   title       = {A SystemC Single-Cycle Simulator},
   school      = {University of California},
   year        = 2011,
   address     = {Davis, CA, USA},
   month       = dec,
   note        = {\url{http://www.ece.ucdavis.edu/vcl/pubs/theses/2011-3/}}
   }