Optimizing Power of Many-Core Systems by Exploiting Dynamic Voltage, Frequency and Core Scaling

Bin Liu
Mohammad H. Foroozannejad
Soheil Ghiasi
Bevan M. Baas

VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

Best Student Paper Award, Third Place at the 58th IEEE Midwest Symposium on Circuits and Systems (MWSCAS), 2015.

Abstract:

To address the well-known "power wall" issue, many-core processors with dynamic voltage and frequency scaling (DVFS) are widely investigated. To further improve the energy efficiency, DVFS with core scaling (DVFCS) has been proposed. In this paper, we address the problem of minimizing the power dissipation of many-core systems under performance constraints by choosing appropriate number of active cores and per-core voltage/frequency levels. A genetic algorithm based solution is proposed to solve the problem. Experiments with real applications show that (1) dynamically scaling the number of active cores can save up to 72% power compared with per-core DVFS; (2) the amount of extra power saving brought by core scaling is highly dependent on performance constraints.

Paper

Reference

Bin Liu, Mohammad H. Foroozannejad, Soheil Ghiasi and Bevan M. Baas, "Optimizing Power of Many-Core Systems by Exploiting Dynamic Voltage, Frequency and Core Scaling," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) Aug. 2015.

BibTeX Entry

@INPROCEEDINGS{Liu:MWSCAS2015,
   author={Bin Liu, Mohammad H. Foroozannejad, Soheil Ghiasi and Bevan M. Baas},
   booktitle={IEEE International Midwest Symposium on Circuits and Systems ({MWSCAS})}, 
   title={Optimizing Power of Many-Core Systems by Exploiting Dynamic Voltage, Frequency and Core Scaling},
   year={2015},
   month={Aug.}
}
VCL Lab | ECE Dept. | UC Davis

Last update: Aug. 7, 2015