Video encoding has become an integral part for everyday computing from televisions and computers to portable devices such as cell phones. Achieving high quality resolution over limited bandwidth has lead to the development of the H.264 video standard providing greater encoding performance. In this work an H.264 baseline video encoder is presented on a fine grained 167-core programmable processor allowing for greater flexibility and parallelization. The encoder presented is capable of encoding QCIF-resolution video at 1.00 GHz while dissipating an average of 438 mW, and CIF-resolution at 1.20 GHz while an average of 787 mW. The Asynchronous Array of Simple Processors (AsAP) platforms provides a new method of coding over a large number of simple processors allowing for a higher level of parallelization than digital signal processors (DSP) while avoiding the complexity of a fully application specific integrated circuit (ASIC).
Stephen T. Le, "A Fine Grained Many-Core H.264 Video Encoder," Technical Report ECE-CE-2010-03, VLSI Computation Laboratory, ECE Department, University of California, Davis, 2010.
@mastersthesis{stle:msthesis,
author = {Stephen T. Le},
title = {A Fine Grained Many-Core H.264 Video Encoder},
school = {University of California},
year = 2010,
address = {Davis, CA, USA},
month = Mar,
note = {\url{http://www.ece.ucdavis.edu/vcl/pubs/theses/2010-03}}
}