Display Stream Compression Decoders for Fine-Grained Many-Core Processor Arrays

Shifu Wu
Bevan M. Baas

Abstract:

This brief presents two software Display Stream Compression (DSC) video decoder designs for many-core processor arrays. The first design exploits fine-grained task-level parallelism and is able to decode pictures configured into one column of slices; it is implemented with 88 processors and 2 shared memory modules. The second design facilitates higher performance by leveraging scalable slice-level parallelism and is tailored for pictures configured into multiple columns of slices; one implementation of this design is mapped to 359 processors and 6 shared memory modules. At 1.75 GHz and 1.1 V, the proposed decoders decode 1080p video sequences in 4:2:0, 4:2:2, and 4:4:4 pixel formats—achieving up to 94.7 frames per second (fps), 95.6 fps, and 47.9 fps, while dissipating 23.9 nJ, 26.7 nJ, and 47.2 nJ per pixel, respectively. Our designs achieve up to 159x higher throughput and 841x lower energy per pixel than a DSC decoder implemented on one core of an Intel i7-7700HQ processor.

Paper

  PDF (1,253 KB)   [IEEE link],   (c) Copyright, 2021, IEEE

Reference

Shifu Wu and Bevan M. Baas, "Display Stream Compression Decoders for Fine-Grained Many-Core Processor Arrays," IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 68, no. 5, pp. 1730–1734, May 2021.

BibTeX Entry

@article{wu:tcasii2021,
   author    = {Shifu Wu and Bevan M. Baas},
   booktitle = {{IEEE} Transactions on Circuits and Systems II: Express Briefs},
   title     = {Display Stream Compression Decoders for Fine-Grained Many-Core Processor Arrays},
   year      = 2021,
   month     = may,
   volume    = {68},
   number    = {5},
   pages     = {1730-1734},
}