Canonical Huffman Decoder on Fine-grain Many-core Processor Arrays

Satyabrata Sarangi
Bevan M. Baas

Abstract:

Canonical Huffman codecs have been used in a wide variety of platforms ranging from mobile devices to data centers which all demand high energy efficiency and high throughput. This work presents bit-parallel canonical Huffman decoder implementations on a fine-grain many-core array built using simple RISC-style programmable processors. We develop multiple energy-efficient and area-efficient decoder implementations and the results are compared with an Intel i7-4850HQ and a massively parallel GT 750M GPU executing the corpus benchmarks: Calgary, Canterbury, Artificial, and Large. The many-core implementations achieve a scaled throughput per chip area that is 324× and 2.7× greater on average than the i7 and GT 750M respectively. In addition, the many-core implementations yield a scaled energy efficiency (bytes decoded per energy) that is 24.1× and 4.6× greater than the i7 and GT 750M respectively.

Paper

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Reference

Satyabrata Sarangi and Bevan M. Baas, "Canonical Huffman Decoder on Fine-grain Many-core Processor Arrays," IEEE/ACM Asia and South Pacific Design Automation Conference, Tokyo, Japan, January, 2021.

BibTeX Entry

@inproceedings{sarangi:aspdac2021,
   author    = {Satyabrata Sarangi and Bevan M. Baas},
   booktitle = {{IEEE/ACM} Asia and South Pacific Design Automation Conference},
   title     = {Canonical Huffman Decoder on Fine-grain Many-core Processor Arrays},
   year      = 2021,
   month     = jan
   }