Indexed Color History Many-Core Engines for Display Stream Compression Decoders

Shifu Wu
Bevan M. Baas

Abstract:

This paper describes and compares 9 many-core designs and software implementations of the Indexed Color History (ICH) module, which is part of VESA Display Stream Compression (DSC) decoders. The smallest design is mapped to only 8 small processors. Other designs use a new algorithm to split the ICH table update process into index update and entry update tasks. This algorithm is implemented with a variety of parallel and optimized architectures to provide a range of throughputs and energy efficiencies utilizing from 9 to 53 processors. The proposed ICH designs deliver frame rates in 1080p (1920×1080) up to 75, 74, and 38 frames per second (fps) in 4:2:0, 4:2:2, and 4:4:4 modes, while dissipating 15 mJ, 16 mJ, and 30 mJ per frame respectively at 1.75 GHz at 1.1 V. Compared to reference designs implemented on an Intel i7-7700HQ, the proposed designs achieve up to 3.4×, 3.9×, and 5.3× higher frame rates, and up to 177×, 193×, and 261× lower energy per frame in 4:2:0, 4:2:2, and 4:4:4 modes respectively.

Paper

  PDF (455 KB)   [IEEE link],   (c) Copyright, 2020, IEEE

Reference

Shifu Wu and Bevan M. Baas, "Indexed Color History Many-Core Engines for Display Stream Compression Decoders," IEEE International Conference on Electronics, Circuits & Systems (ICECS), Glasgow, Scotland, November, 2020.

BibTeX Entry

@inproceedings{wu:icecs2020,
   author    = {Shifu Wu and Bevan M. Baas},
   booktitle = {{IEEE} International Conference on Electronics, Circuits and Systems},
   title     = {Indexed Color History Many-Core Engines for Display Stream Compression Decoders},
   year      = 2020,
   month     = nov
   }