A Low-Cost Slice Interleaving DSC Decoder Architecture for Real-Time 8K Video Decoding

Shifu Wu
Bevan M. Baas

VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

Abstract:

High resolution and high frame rate video including 4K and 8K is increasingly popular, however its real-time decoding using H.264 and HEVC is challenging due to its high hardware computational cost and large memory requirement. In contrast, the Display Stream Compression (DSC) video decoder requires much smaller hardware and easily supports very high pixel rates. We present a low-cost DSC decoder utilizing a slice interleaving architecture, as well as four designs that utilize the architecture implemented and synthesized in a 28 nm CMOS standard cell process. The designs are able to perform real-time decoding at frame rates up to 94–107 frames per second (fps) for 8K UHD and 376–430 fps for 4K UHD, both in 4:4:4 mode with a throughput of 3 pixels per clock cycle. The frame rates are doubled in native 4:2:2 and 4:2:0 modes. The designs have gate counts of 161K–282K in minimum-sized NAND2 equivalent gates and main memory of 36.9KB–54.7KB to support 8K UHD.

Paper

Reference

Shifu Wu and Bevan M. Baas, "A Low-Cost Slice Interleaving DSC Decoder Architecture for Real-Time 8K Video Decoding," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2018.

BibTeX Entry

@INPROCEEDINGS{Wu:MWSCAS2018,
   author={Shifu Wu and Bevan M. Baas},
   booktitle={IEEE International Midwest Symposium on Circuits and Systems ({MWSCAS})}, 
   title={A Low-Cost Slice Interleaving DSC Decoder Architecture for Real-Time 8K Video Decoding},
   year={2018},
   month={Aug.}
}
VCL Lab | ECE Dept. | UC Davis

Last update: Aug. 26, 2018