Achieving High-Performance On-Chip Networks With Shared-Buffer Routers

VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

Abstract:

On-chip routers typically have buffers dedicated to their input or output ports for temporarily storing packets in case contention occurs on output physical channels. Buffers, unfortunately, consume significant portions of router area and power budgets. While running a traffic trace, however, not all input ports of routers have incoming packets needed to be transferred simultaneously. Therefore, a large number of buffer queues in the network are empty and other queues are mostly busy. This observation motivates us to design router architecture with shared queues (RoShaQ), router architecture that maximizes buffer utilization by allowing the sharing multiple buffer queues among input ports. Sharing queues, in fact, makes using buffers more efficient hence is able to achieve higher throughput when the network load becomes heavy. On the other side, at light traffic load, our router achieves low latency by allowing packets to effectively bypass these shared queues. Experimental results on a 65 nm CMOS standard-cell process show that over synthetic traffics RoShaQ has 17% less latency and 18% higher saturation throughput than a typical virtualchannel (VC) router. Because of its higher performance, RoShaQ consumes 9% less energy per transferred packet than VC router given the same buffer space capacity. Over real multitask applications and E3S embedded benchmarks using near-optimal NMAP mapping algorithm, RoShaQ has 32% lower latency than VC router and targeting the same application throughput with 30% lower energy per packet.

Paper

PDF (2.0 MB)

Reference

Anh T. Tran and Bevan M. Baas, "Achieving High-Performance On-Chip Networks With Shared-Buffer Routers," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 22, no. 6, pp. 1391–1403, June 2014. (Official date of publication July 3, 2013.)

Note on Publication Date

Although the official publication date of this paper is July 3, 2013, it did not appear in print until the June 2014 issue of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI).

"Manuscript received October 20, 2012; revised May 24, 2013; accepted June 9, 2013. Date of publication July 3, 2013; date of current version May 20, 2014."

BibTeX Entry

@article{tran:tvlsi:2013,
   author    = {Anh T. Tran and Bevan M. Baas},
   title     = {Achieving High-Performance On-Chip Networks With Shared-Buffer Routers},
   journal   = {IEEE Transactions on Very Large Scale Integration Systems (TVLSI)},
   month     = jun,
   year      = 2014,
   volume    = 22,
   number    = 6,
   pages     = {1391--1403},
   note      = {Official date of publication July 3, 2013}
   }

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Last update: August 8, 2014