2-Dimensional meshes are the most commonly used Network-on-Chip (NoC) topology for on-chip communication in many-core processor arrays due to their low complexity and excellent match to rectangular processor tiles. tile-based layout property. However, 2D meshes may incur local traffic congestion for applications with significant levels of traffic with non-neighboring cores, resulting in long latencies and high power consumption. In this paper, we propose an 8-neighbor mesh topology and a 6-neighbor topology with hexagonal-shaped processor tiles. for many-core processor arrays. A 16-bit DSP processor and the corresponding processor arrays are implemented in all three topologies. The hexagonal processor tile and arrays of tiles are laid out using industry-standard CAD tools and automatic place and route flow without full-custom design, and result in DRC-clean and LVS-clean layout. A 1080p H.264/AVC residual video encoder and a 54 Mbps 802.11a/11g OFDM wireless LAN baseband receiver are mapped onto all topologies. The 6-neighbor hexagonal grid topology incurs a 2.9% area increase per tile compared to the 4-neighbor 2D mesh, but its much more effective inter-processor interconnect yields an average total application area reduction of 21%, an average power reduction of 17%, and a total application inter-processor communication distance reduction of 19%.
Zhibin Xiao and Bevan Baas, "A Hexagonal Shaped Processor and Interconnect Topology for Tightly-tiled Many-core Architecture," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2012.
@INPROCEEDINGS{zhibin:vlsi-soc2012, author = {Zhibin Xiao and Bevan Baas}, booktitle = {IFIP/IEEE Internation Conference on Very Large Scale Integration (VLSI-SoC)}, title = {A Hexagonal-Shaped Processor and Interconnect Topology for Tightly-tiled Many-core Architecture}, year = 2012, month = Oct. }
Last update: July 20, 2012