Introduction to the Special Issue: Hot Chips 23

Abstract:

We've seen this in Hot Chips over the years with reduced-instruction-set computing (RISC) versus complex-instruction-set computing (CISC), new instruction set architectures, instruction set parallelism, graphics and video processors, very long instruction word (VLIW) and digital signal processing (DSP) architectures, network processors, and the growing trend of entire systems, including servers, on a chip.

Many cores, many threads, much power

Hot Chips 23 was clearly the year of many-core and many-thread processors (either sharing core hardware or as a separate many-core chip, or even as partially shared cores); there wasn't a product category that didn't have that as a defining feature. The products presented stood out not by their sheer number of threads, but by the way the cores and threads communicated and synchronized, and the architectural innovations that enabled the threads to be efficiently used.

But the parallelism enabled by multiple threads isn't enough in a new world of power constraints. The product innovations presented at Hot Chips specifically targeted the conflicting goals of keeping threads as busy as possible, while using as little power as possible.

Paper

  PDF (831 KB),   (c) Copyright, 2012, IEEE

Reference

A. Baum and B. M. Baas, "Introduction to the Special Issue: Hot Chips 23," IEEE Micro, March/April 2012.

BibTeX Entry

@article{baum:micro:2012,
   author    = {Allen Baum and Bevan Baas},
   title     = {Introduction to the Special Issue: Hot Chips 23},
   journal   = {IEEE Micro},
   year      = 2012,
   month     = mar,
   pages     = {6-7},
   volume    = 32,
   number    = 2
   }