Processor Shapes and Topologies for Dense On-Chip Networks

Zhibin Xiao
Bevan M. Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

Abstract:

Interconnection topologies greatly affect the performance, energy efficiency, and circuit area of many-core processor arrays. Simple topologies such as buses, rings and 2-dimensional (2D) meshes are commonly utilized due to their simplicity of physical implementation. This work proposes novel processor shapes and interconnection topologies for many-core processor arrays that include two 5-neighbor, three 6-neighbor and two 8-neighbor topologies three of which utilize house-shaped and hexagonal-shaped processor tiles. Two complete complex applications are mapped onto both the 2D mesh and the hexagonal array -- 25-processor 1080p H.264/AVC video residual encoder and a 24-processor 802.11a/11g wireless LAN baseband receiver. The hexagonal-shaped processor tiles and array are built with industry-standard CAD tools, an automatic place and route flow without full-custom layout, and regular Manhattan routing. Compared to the 2D mesh, both the 6-neighbor hexagonal and the 6-neighbor rectangular tile incur a 2.9% area penalty per tile, but their much more effective inter-processor interconnect yields an average total application area reduction of 21%, and a total application inter-processor communication distance reduction of 19%.

Poster

Brief Slide Overview

PPT (0.6 MB), 2 slides

Reference

Zhibin Xiao and Bevan Baas, "Processor Shapes and Topologies for Dense On-chip Networks," presented in the IEEE International Solid-Sate Circuit Conference (ISSCC 2012) Student Forum, San Francisco, CA, Feb. 2012.

VCL Lab | ECE Dept. | UC Davis

Last update: Feb 2, 2012