A Fine-grained Parallel Implementation of a H.264/AVC Encoder on a 167-processor Computational Platform
Zhibin Xiao
Stephen Le
Bevan Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis
Abstract:
The emerging many-core architecture provides a flexible solution for
the rapid evolving multimedia applications demanding both high
performance and high energy-efficiency. However, developing parallel
multimedia applications that can efficiently harness and utilize many-core
architectures is the key challenge for scalable computing. We
contribute to this challenge by presenting a fully-parallel H.264/AVC baseline
encoder on a 167-core asynchronous array of simple processors(AsAP) computation platform.
By exploiting fine-grained data and task level parallelism
in the algorithms, we partition and map the dataflow of the H.264/AVC
encoder to an array of 115 small processors coupled with two shared
memories and a hardware accelerator for motion estimation.
The proposed parallel H.264/AVC encoder is capable of encoding video sequences with variable frame sizes.
The encoder presented is capable of encoding VGA (640x480) video at
21 frames per second (fps) with 931 mW average power consumption by
adjusting each processor to workload-based optimal clock frequencies
and dual supply voltages with less than 1 dB loss in resolution.
Paper
Presentation
Reference
Zhibin Xiao, Stephen Le and Bevan Baas,
"A Fine-grained Parallel Implementation of a H.264/AVC Encoder on a 167-processor Computational Platform,"
IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC),
Pacific Grove, CA, November 2011.
BibTeX Entry
@INPROCEEDINGS{ZBXiao:Asilomar2011,
author = {Zhibin Xiao and Stephen Le and Bevan Baas},
booktitle = {IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC)},
title = {A Fine-grained Parallel Implementation of a {H.264/AVC} Encoder on a 167-processor Computational Platform},
year = 2011,
month = nov
}
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Last update: Nov. 17, 2011