A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders

Abstract:

A Split decoding algorithm is proposed which
divides each row of the parity check matrix into two or
multiple nearly-independent simplified partitions. The
proposed method significantly reduces the wire interconnect
and decoder complexity and therefore results
in fast, small, and high energy efficiency circuits. Three
full-parallel decoder chips for a (2048, 1723) LDPC
code compliant with the 10GBASE-T standard using
MinSum normalized, MinSum Split-2, and MinSum
Split-4 methods are designed in 65 nm, seven metal
layer CMOS. The Split-4 decoder occupies 6.1 mm2,
operates at 146 MHz, delivers 19.9 Gbps throughput,
with 15 decoding iterations. At 0.79 V, it operates at
47 MHz, delivers 6.4 Gbps and dissipates 226 mW.
Compared to MinSum normalized, the Split-4 decoder
chip is 3.3 times smaller, has a clock rate and throughput
2.5 times higher, is 2.5 times more energy efficient,
and has an error performance degradation of 0.55 dB
with 15 iterations.

Paper

  PDF (851 KB),   (c) Copyright, 2010, Springer

Reference

Tinoosh Mohsenin; Baas, B.M.; , "Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders,"
Journal of Signal Processing Systems for Signal, Image, and Video Technology, available online, Feb. 2010.

BibTeX Entry

@article {Mohsenin:JSPS,
   author = {Mohsenin, Tinoosh and Baas, Bevan},
   affiliation = {University of California, Davis Department of Electrical and Computer Engineering 95616 Davis CA USA},
   title = {A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders},
   journal = {Journal of Signal Processing Systems},
   publisher = {Springer New York},
   issn = {1939-8018},
   keyword = {Electrical Engineering},
   url = {http://dx.doi.org/10.1007/s11265-010-0456-y},
   note = {10.1007/s11265-010-0456-y},
   year = {2010},
   month = {Feb.}
}