A Low-Area Interconnect Architecture for Chip Multiprocessors

Zhiyi Yu
Bevan M. Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

Abstract:

A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost and flexible routing capability. To achieve a low area cost, the proposed statically-configurable asymmetric architecture assigns large buffer resources only to the nearest neighbor interconnect and much smaller buffer resources for long distance interconnect. To maintain flexible routing capability, each neighboring processor pair has two connecting links. Compared to a traditional dynamically-configurable interconnect architecture with symmetric buffer allocation and single-links between neighboring processor pairs, this implementation has approximately 2 times smaller communication circuitry area with a similar routing capability. Area and speed estimates are obtained with the physical design of seven chips in 0.18 μm CMOS.

Paper

Presentation Slides

Reference

Zhiyi Yu and Bevan M. Baas. "A Low-Area Interconnect Architecture for Chip Multiprocessors" In Proceedings of The IEEE International Symposium on Circuits and Systems (ISCAS), May 2008, pp. 2857-2860.

BibTeX entry

@inproceedings{UCDVCL:2008:ISCAS_NoC,
   author    = {Zhiyi Yu and Bevan M. Baas},
   title     = {A Low-Area Interconnect Architecture for Chip Multiprocessors}, 
   booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},
   month     = may,
   year      = 2008,
   pages     = {2857-2860}
   }
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Last update: March 24, 2009