A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains

Abstract:

A robust, scalable, and power efficient dual-clock first-input first-out (FIFO) architecture which is useful for transferring data between modules operating in different clock transferring data between modules operating in different clock operation in applications where multiple clock cycles of latency exist between the data producer, FIFO, and the data consumer; and with arbitrary clock frequency changes, halting, and restarting in either or both clock domains. The architecture is demonstrated in both a 0.18 μm CMOS full-custom design and a 0.18 μm CMOS standard cell design used in a globally asynchronous locally synchronous array processor. It achieves 580 MHz operation and 10.3 mW power dissipation while performing simultaneous FIFO READ and WRITE operations at 1.8 V.

Paper

  PDF (2.1 MB),   [IEEE link],   (c) Copyright, 2007 IEEE

Reference

Ryan Apperson, Zhiyi Yu, Michael Meeuwsen, Tinoosh Mohsenin, Bevan Baas, "A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 15, no. 10, pp. 1125-1134, October 2007.

BibTeX entry

@article{VCL:TVLSI:2007,
   author    = {Ryan Apperson and Zhiyi Yu and Michael Meeuwsen and Tinoosh Mohsenin and Bevan Baas},
   title     = {A Scalable Dual-Clock {FIFO} for Data Transfers Between Arbitrary and Haltable Clock Domains},
   journal   = {IEEE Transactions on Very Large Scale Integration Systems (TVLSI)},
   year      = 2007,
   month     = oct,
   pages     = {1125-1134},
   volume    = 15,
   number    = 10
   }

Last update: November 8, 2007