This paper investigates implementation techniques for tile-based chip multiprocessors with Globally Asynchronous Locally Synchronous (GALS) clocking styles. These architectures can simplify the physical design flow since they allow focusing on a single processor when designing an entire chip. However, they also introduce challenges to maintain system robustness and scalability. We propose a physical design flow for these architectures, investigate timing issues for robust implementations, and propose methods to take full advantage of their potential scalability. As a design example, we present data from a recently implemented single-chip 6 x 6 tile-based GALS processing array.
Zhiyi Yu, Bevan M. Baas. "Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles" In Proceedings of The IEEE International Conference of Computer Design (ICCD) , October 2006, pp.174-179.
@inproceedings{UCDVCL:2006:ICCD1,
author = {Zhiyi Yu and Bevan M. Baas},
title = {Implementing Tile-based Chip Multiprocessors with GALS
Clocking Styles},
booktitle = {IEEE International Conference of Computer Design (ICCD)},
month = October,
year = 2006
}
Last update: September 08, 2006